About the role
You turn a proven architectural idea into hardware that computes correctly: the digital logic for an accelerator or subsystem we have justified. The justification matters, because we do not build silicon speculatively, and the work starts once the measurement says it is worth it.
The work
Develop synthesizable RTL, interfaces, control logic and power-aware behavior. Work with verification, compiler and physical-design engineers from the beginning. Track area, frequency and energy against a documented workload and resist optimizing a benchmark that does not represent the product.
What good looks like
In your first 90 days after program activation, deliver a verified block prototype with synthesis results and a traceable specification.
Evidence we look for
Bring digital design fundamentals, SystemVerilog or equivalent RTL experience, and strong reasoning about pipelines, resets, clock domains and backpressure.
What we need to see
- Digital design fundamentals and RTL experience in SystemVerilog or equivalent
- Strong reasoning about pipelines, resets, clock domains and backpressure
- You design for verifiability rather than leaving that to somebody downstream
- You have taped out, or taken a design to a comparable point of commitment
Nice to have
- Accelerator or datapath design specifically
- Low-power design techniques
- You have worked closely with a verification team and improved how they could test your work
The exercise
Review a small streaming datapath for correctness under stalls, reset and malformed input before discussing throughput.
Where and how we work
In the office together five days a week, in any of these cities. Remote-friendly around your family, arranged one person at a time.